Ignitarium is a Silicon and Embedded System design house, formed with the vision to provide innovative, optimal and relevant solutions for enabling and assisting their customers in product development. Ignitarium is built around a core team of technologists, who share a collective industry experience of over 150 years with expertise in system architecture, logic design and verification, signal processing, FPGA design, embedded system design and associated software development.

Practice Head- Physical DesignResponsibilitiesIgnitarium is hiring a practice head for physical design stream for the semiconductor division. The semiconductor team offers cutting-edge ASIC, SoC and FPGA solutions to problems in the automotive, embedded compute, consumer electronics and communication space. As a practice head you will be responsible for defining methodology, work on complex full chip implementations for marquee projects, ensuring competency of the entire team and working on physical design proposals. The candidate should be well versed with lower nodes preferably upto 5nm. The individual should be knowledgeable of full chip PD flow and should be able to comprehend nuances with respect to front end design, DFT and system design to work seamlessly with these teams to ensure the functional, performance and power goals of the chip are met. The candidate should be knowledgeable of IO planning, complex power architecture,&nbsp;place and route, timing closure, DRC and LVS checks. The candidate should have worked on high speed designs and interfaces like DDR, HBM and Serdes and should have hands on experience in closing timing for these. He should be a master scripter and should continuously automate flows to ensure higher productivity in execution.A leader who is experienced and curious, who has a never-ending appetite for learning, and who can solve problems with a "never give up" mentality, would be perfect. The individual will collaborate with teams from several domains while utilising their varied skill sets. He/She will also be responsible for competency of the entire team and will work towards building capabilities of the team. Therefore, the individual should be a good mentor and a teacher. &nbsp;He/She should drive hiring initiatives and also focus on building large and capable teams meeting the customer’s challenges.QualificationsElectrical engineering or electronics engineering Btech, MTech or PhD degree10 years of relevant experience in the conception through to production of high speed ASICsShould have worked on lower technology nodes ideally 10nm and belowShould have done hands on work in full chip PD flow including IO planning, power planning, Place and Route, Timing closure, DRC and LVS.Requires practical knowledge of all phases of VLSI development as well as a track record of working with different stakeholders like architecture, software, design, dft and foundry services to ensure careabouts of other domains are understood and addressed.

Practice Head- DFTResponsibilitiesIgnitarium is hiring a practice head for Design For Test stream for the semiconductor division. The semiconductor team offers cutting-edge ASIC, SoC and FPGA solutions to problems in the automotive, embedded compute, consumer electronics and communication space. As a practice head you will be responsible for defining methodology, work on complex full chip implementations for marquee projects, ensuring competency of the entire team and working on DFT proposals. The candidate should have handled large blocks with multi-million gates, containing many clock domains, memory and analog macros. The individual should be knowledgeable of full chip DFT flow and should be able to comprehend nuances with respect to front end design, Physical design and system design to work seamlessly with these teams to ensure the DFT goals are met. The candidate should be knowledgeable of Boundary scan, MBIST, LBIST, Scan insertion, ATPG pattern generation and validation, Gate level simulation, EDT and OCC insertion and debugging failures in the tester. The candidate should have worked on Synopsys, Mentor and Cadence tool flows. He should be a master scripter and should continuously automate flows to ensure higher productivity in execution.A leader who is experienced and curious, who has a never-ending appetite for learning, and who can solve problems with a "never give up" mentality, would be perfect. The individual will collaborate with teams from several domains while utilising their varied skill sets. He/She will also be responsible for competency of the entire team and will work towards building capabilities of the team. Therefore, the individual should be a good mentor and a teacher. &nbsp;He/She should drive hiring initiatives and also focus on building large and capable teams meeting the customer’s challenges.QualificationsElectrical engineering or electronics engineering Btech, MTech or PhD degree10 years of relevant experience in multiple flows in DFT which includes boundary scan, MBIST, LBIST, Scan insertion, ATPG pattern generation and validation, Gate level simulation, EDT and OCC insertion and debugging failures in the tester.Should have worked on large multi million gate designs handling multiple blocks at the same timeShould have worked on industry leading tools from Synopsys, Mentor and CadenceRequires practical knowledge of all phases of VLSI development as well as a track record of working with different stakeholders like architecture,&nbsp;design and PD to ensure careabouts of other domains are understood and addressed.

Skills and Experience&nbsp;RequiredHands on experience in Inserting Scan and generating ATPG vectors forStuck-At and At-Speed Faults. In-depth experience in analysing and&nbsp;improving scan coverageHands on experience in MBIST (insertion and simulation)Experience in Boundary Scan, inserting tap controller and P1500Experience in RTL based and netlist-based insertion flowsExperience in DFT simulation with and without SDF&nbsp;Experience in Synthesis and formal verification toolsExperience in characterization (DC Characteristics)Experience in generating TDL for ATE and working closely with ATE team&nbsp;during bring-up phaseGood exposure to DFT tools from Mentor, Synopsys and CadenceGood scripting know-how in Perl and TCLExperience in Static Timing analysis preferredEducational Qualification: BE/ME or BTech /MTech

<ul><li>Strong programming skills in C</li><li>Embedded Application programming development using C (Verification - Security / Safety Analysis) + C Programming) – SDET (Developer Profiles)</li><li>Next generation automotive platforms (ADAS)</li><li>Good hands-on experience in debugging complex system issues</li><li>Exposure to embedded software and drivers</li><li>Experience with hardware interfaces like i2c, spi, uart, USB etc</li><li>Good to have hands-on experience working in any RTOS (QNX) / Linux</li><li>Good to have skills in Python</li><li>Good to have hands-on experience, working in the Linux kernel &amp;&nbsp;Linux kernel device drivers.</li></ul>&nbsp;

Ignitarium

Practice Head- Physical Design

Practice Head- DFT

DFT Engineer

Software Engineer