Practice Head- DFT

Responsibilities

Ignitarium is hiring a practice head for Design For Test stream for the semiconductor division. The semiconductor team offers cutting-edge ASIC, SoC and FPGA solutions to problems in the automotive, embedded compute, consumer electronics and communication space. As a practice head you will be responsible for defining methodology, work on complex full chip implementations for marquee projects, ensuring competency of the entire team and working on DFT proposals. The candidate should have handled large blocks with multi-million gates, containing many clock domains, memory and analog macros. The individual should be knowledgeable of full chip DFT flow and should be able to comprehend nuances with respect to front end design, Physical design and system design to work seamlessly with these teams to ensure the DFT goals are met. The candidate should be knowledgeable of Boundary scan, MBIST, LBIST, Scan insertion, ATPG pattern generation and validation, Gate level simulation, EDT and OCC insertion and debugging failures in the tester. The candidate should have worked on Synopsys, Mentor and Cadence tool flows. He should be a master scripter and should continuously automate flows to ensure higher productivity in execution.

A leader who is experienced and curious, who has a never-ending appetite for learning, and who can solve problems with a "never give up" mentality, would be perfect. The individual will collaborate with teams from several domains while utilising their varied skill sets. He/She will also be responsible for competency of the entire team and will work towards building capabilities of the team. Therefore, the individual should be a good mentor and a teacher.  He/She should drive hiring initiatives and also focus on building large and capable teams meeting the customer’s challenges.

Qualifications

Electrical engineering or electronics engineering Btech, MTech or PhD degree

10 years of relevant experience in multiple flows in DFT which includes boundary scan, MBIST, LBIST, Scan insertion, ATPG pattern generation and validation, Gate level simulation, EDT and OCC insertion and debugging failures in the tester.

Should have worked on large multi million gate designs handling multiple blocks at the same time

Should have worked on industry leading tools from Synopsys, Mentor and Cadence

Requires practical knowledge of all phases of VLSI development as well as a track record of working with different stakeholders like architecture, design and PD to ensure careabouts of other domains are understood and addressed.