Practice Head- Physical Design

Responsibilities

Ignitarium is hiring a practice head for physical design stream for the semiconductor division. The semiconductor team offers cutting-edge ASIC, SoC and FPGA solutions to problems in the automotive, embedded compute, consumer electronics and communication space. As a practice head you will be responsible for defining methodology, work on complex full chip implementations for marquee projects, ensuring competency of the entire team and working on physical design proposals. The candidate should be well versed with lower nodes preferably upto 5nm. The individual should be knowledgeable of full chip PD flow and should be able to comprehend nuances with respect to front end design, DFT and system design to work seamlessly with these teams to ensure the functional, performance and power goals of the chip are met. The candidate should be knowledgeable of IO planning, complex power architecture, place and route, timing closure, DRC and LVS checks. The candidate should have worked on high speed designs and interfaces like DDR, HBM and Serdes and should have hands on experience in closing timing for these. He should be a master scripter and should continuously automate flows to ensure higher productivity in execution.

A leader who is experienced and curious, who has a never-ending appetite for learning, and who can solve problems with a "never give up" mentality, would be perfect. The individual will collaborate with teams from several domains while utilising their varied skill sets. He/She will also be responsible for competency of the entire team and will work towards building capabilities of the team. Therefore, the individual should be a good mentor and a teacher.  He/She should drive hiring initiatives and also focus on building large and capable teams meeting the customer’s challenges.

Qualifications

Electrical engineering or electronics engineering Btech, MTech or PhD degree

10 years of relevant experience in the conception through to production of high speed ASICs

Should have worked on lower technology nodes ideally 10nm and below

Should have done hands on work in full chip PD flow including IO planning, power planning, Place and Route, Timing closure, DRC and LVS.

Requires practical knowledge of all phases of VLSI development as well as a track record of working with different stakeholders like architecture, software, design, dft and foundry services to ensure careabouts of other domains are understood and addressed.