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Roles and Responsibilties:&nbsp;&nbsp;&nbsp;&nbsp;To play the role of Verification engineer at the Block level, Chip level Functional verification.·&nbsp;&nbsp;&nbsp;&nbsp;Develop verification test plans from design specifications·&nbsp;&nbsp;&nbsp;&nbsp;Development of test environments using System Verilog and UVM verification methodologies.·&nbsp;&nbsp;&nbsp;&nbsp;Create multiple test cases as per the test plan and launch regressions.·&nbsp;&nbsp;&nbsp;&nbsp;Generate Code/Functional coverage, analyze coverage results and correlate with the test plan.·&nbsp;&nbsp;&nbsp;&nbsp;Working with the design team members to identify and quickly resolve problems with the design.·&nbsp;&nbsp;&nbsp;&nbsp;Communicate regularly with the team members to resolve issues and report status.·&nbsp;&nbsp;&nbsp;&nbsp;Bring a self-motivated and enthusiastic approach that will achieve any new requirements and overcome all challenges.&nbsp;Note: If you have attended before please try after 2 months&nbsp;Candidates are to go through the below links to prepare for our interview process&nbsp;<ul><li>Technical and logical questions will be asked from the below link, Please revise accordingly.</li></ul> Eligibility criteria:&nbsp;&nbsp;&nbsp;U.G - B.E/ B. Tech - ECE, EEE, CSE, IT&nbsp;- Upto 2020 PassoutsP.G - M.E / M.TECH VLSI, Embedded, Power Electronics, Applied Electronics, etc - Upto 2022 Passouts

Edveon Technologies

Chip Verification Engineer