Roles and Responsibilties:

    To play the role of Verification engineer at the Block level, Chip level Functional verification.

·    Develop verification test plans from design specifications

·    Development of test environments using System Verilog and UVM verification methodologies.

·    Create multiple test cases as per the test plan and launch regressions.

·    Generate Code/Functional coverage, analyze coverage results and correlate with the test plan.

·    Working with the design team members to identify and quickly resolve problems with the design.

·    Communicate regularly with the team members to resolve issues and report status.

·    Bring a self-motivated and enthusiastic approach that will achieve any new requirements and overcome all challenges.

Note: If you have attended before please try after 2 months

Candidates are to go through the below links to prepare for our interview process

• Technical and logical questions will be asked from the below link, Please revise accordingly.

Eligibility criteria:  

U.G - B.E/ B. Tech - ECE, EEE, CSE, IT - Upto 2020 Passouts

P.G - M.E / M.TECH VLSI, Embedded, Power Electronics, Applied Electronics, etc - Upto 2022 Passouts