Company Overview

Proxelera’s unmatched expertise in VLSI design is expanding into new frontiers in the international market. Our business operations are making an entry into the Israeli market aggressively, heralding a new milestone. In this regard, we have signed up with the Israeli company, TechLink Global Ltd, based out of Tel Aviv. Proxelera’s presence in one of the most technologically advanced countries in the world stands as a testimony to our technical prowess in the VLSI and semiconductor industry. Our headquarters are located in Bangalore, and we belong to the Semiconductors industry.

Job Overview

We are seeking a dynamic and experienced STA Engineer to join our team in Bengaluru or Hyderabad. The successful candidate will play a crucial role in our VLSI design projects, performing static timing analysis to ensure the robustness and reliability of our designs. This is a mid-level, full-time position offering a unique opportunity to be part of a leading technology company in the semiconductor industry.

Qualifications and Skills

• Proficiency in Static Timing Analysis (Mandatory skill)
• Experience in Timing Closure to optimize and ensure design meets required specifications
• Understanding of Clock Domain Crossing to manage timing across asynchronous clock domains
• Knowledge of Synthesis for converting high-level design descriptions into gate-level representations
• Proficiency in Scripting languages such as Tcl, Perl, and Python for automating workflows
• Familiarity with Signal Integrity to ensure signal quality and minimize issues like noise and crosstalk
• Experience in Low Power Design to create energy-efficient VLSI designs
• Ability to define and apply Timing Constraints to ensure design meets performance requirements

Roles and Responsibilities

• Perform static timing analysis and validation of complex VLSI designs
• Work closely with design and verification teams to resolve timing issues
• Develop and maintain timing constraints and guidelines for design projects
• Identify and analyze potential timing bottlenecks and propose solutions
• Support timing closure activities through synthesis and place-and-route cycles
• Collaborate with cross-functional teams to ensure the robustness of clock domain crossings
• Automate repetitive tasks using scripting languages to enhance productivity
• Ensure designs meet all signal integrity and low power design requirements