Company Overview

Proxelera’s unmatched expertise in VLSI design is expanding into new frontiers in the international market. Our business operations are making an entry into the Israeli market aggressively, heralding a new milestone. In this regard, we have signed up with the Israeli company, TechLink Global Ltd, based out of Tel Aviv. We are confident that this venture will be profitable in more ways than one for both partners. Proxelera’s presence in one of the most technologically advanced countries in the world stands as a testimony to our technical prowess in the VLSI and semiconductor industry. PROXELRA has 51-200 employees. The company website is https://proxelera.com/. The headquarter is located in Bangalore. The company belongs to the Semiconductors industry.

Job Overview

We are looking for a motivated RTL Design Engineer to join our team in Bangalore Urban. This is a full-time, mid-level position that requires a minimum of 4 years and a maximum of 6 years of relevant work experience. As an RTL Design Engineer at Proxelera, you will be an integral part of our VLSI design team, driving our semiconductor solutions to new heights.

KEY RESPONSIBILITIES: 

• Understand RTL at structural level, IP boundaries, IP parameters.
• Understand IP design.
• Add assertions where needed.
• Generate various constraints necessary for the IP.
• RTL build flow setup and maintenance.
• Do the quality checks of the IP like Lint/CDC/RDC/Synth/Timing checks/waiver creation across milestones.
• Participate in IP integration to the subsystem level.
• Write sample test bench to verify the basic functionality of the IP/block.
• Do the first level of triage of the functional issues reported.
• Understand the reports out of quality checks such as Lint/CDC/RDC/Synth/Timing checks and suggest fix in the RTL
• Work with functional verification team to meet coverage and quality standards.
• Guarantee quality/timely deliverables meeting project’s schedule.
• Help to improve/automate design process.

PREFERRED EXPERIENCE: 

• Knowledge of ASIC development flows
• Knowledge of front-end RTL design tools and methodologies.
• Knowledge of system verilog
• Multi-clock domain designs.
• Design constraints for synthesis and static timing analysis.
• Experience in rtl linting tools, reset domain crossings, clock domain crossings, synthesis, RAM generation (area, timing, power)
• Knowledge of AXI/AMBA protocol
• Knowledge of front-end requirements and deliverables for verification, validation, physical design, architecture, security, dfx, power.
• Verification - coverage, test plan, debug
• Physical design – timing, clock crossings, reset crossings, ECOs (manual, formal)
• Ability to work and effectively collaborate with partners
• Knowledge of scripting languages like Perl, tcl or cshell
• Experience with DMAs, PCIe, ordering, datapath virtualization, performance, flow control a plus.