·Must have hands on designed/implemented/Integrated DDR controller or DDR Phy design for a project(ASIC or FPGA).

·Should be excellent in DDR protocol knowledge.

·Must be an expert in micro architecture and RTL coding.

·Skill set needed – Verilog, SoC & Sub-system RTL Integration, knowledge of industry known standards Interfaces (AXI, AMBA, NOC, Fabric, UCIE, PCIE, SATA, DDR etc. etc.)

·Scripting (Shell, python, ruby, perl etc.), CDC & LINT Checkers, Synthesis, LEC, Constraints/SDC understanding, Clocking, UPF, Register roll up.