IC design implementation from RTL to netlist including synthesis, timing constraint composing

IC physical implementation from netlist to GDSII, including floor planning, power grid implementation, place and route, clock tree synthesis, timing ECO, design closure

IC design verification including timing analysis, timing signoff, formal verification and low power verification.

IC physical verification including physical verification, crosstalk analysis, power analysis, ESD analysis, EM analysis

mail to: pavan.pv@proxelera.com

https://proxelera.com/