Memory Layout Engineer
Memory Layout Engineer39
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39
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About the Job
Skills
Company Overview
Proxelera’s unmatched expertise in VLSI design is expanding into new frontiers in the international market. Our business operations are making an entry into the Israeli market aggressively, heralding a new milestone. TechLink Global Ltd, based out of Tel Aviv, is our representative in Israel. Proxelera’s presence in one of the most technologically advanced countries in the world stands as a testimony to our technical prowess in the VLSI and semiconductor industry. Proxelera has 51-200 employees and is headquartered in Bengaluru. The company belongs to the Semiconductors industry. Visit our website.
Job Overview
We are seeking a highly skilled and experienced Memory Layout Engineer to join our team at Proxelera. This is a Senior level, full-time position based in Bengaluru, requiring 7 to 10 years of relevant work experience. The ideal candidate will be responsible for designing high-performance, low-power memory layouts, ensuring effective memory architecture, and collaborating closely with cross-functional teams.
Job Description:
- Memory Layout Design: Create and optimize layouts for various types of memory, including SRAM, DRAM, Flash, and other non-volatile memories.
- Layout Verification: Perform layout verification using DRC (Design Rule Checking), LVS (Layout Versus Schematic), and ERC (Electrical Rule Checking) to ensure design accuracy and adherence to manufacturing requirements.
- Collaboration: Work closely with circuit designers, process engineers, and CAD tool engineers to ensure that layout designs meet all electrical and physical requirements.
- Optimization: Optimize memory cell layouts for performance, power, and area efficiency.
- Technology Evaluation: Evaluate new process technologies and contribute to technology development by providing feedback on design rules and process capabilities.
- Documentation: Maintain thorough documentation of design processes, methodologies, and best practices.
- Mentorship: Provide guidance and mentorship to junior layout designers.
- Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment.
- Contribute to effective project-management.
Qualifications
- Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- Experience:
- Proven experience in memory layout design.
- Familiarity with advanced CMOS process technologies.
- Experience with EDA tools such as Cadence Virtuoso, Synopsys ICC, Mentor Graphics Calibre, etc.
About the company
Industry
Semiconductors
Company Size
51-200 Employees
Headquarter
BANGALORE
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