THE ROLE:

The position will involve working with a very experienced circuit design team of CPU core macros and is responsible for delivering the macro design to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology.

THE PERSON:

Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player.

KEY RESPONSIBILITIES:

• Good Understanding of SRAM, ROM and digital circuit design
• Implementing Design Schematic
• Circuit design and debug
• Silicon issue debug
• Statistical analysis of design
• Logical equivalence check of design
• Handling Internal timings, Power, Leakage, Crosstalk Analysis(noise), Electromigration, IR drop
• Handling different design tools – Cadence Virtuoso, Formality, ESP-CV, NanoTime, Hspice, StarRC, Mentor Graphics Calibre

PREFERRED EXPERIENCE:

• 5+ years of professional experience in SRAM/ROM design, preferably with high performance memory circuit designs.
• Experience in high-speed SRAM design, mainly L1, L2 and L3 design
• Experience in checks for logic equivalence
• Versatility with scripts to automate design flow.
• Strong communication skills, ability to multi-task across projects, and work with geographically spread-out teams
• Experience in FinFET & Dual Patterning nodes such as 7/5/3nm
• Excellent layout understanding.
• Good understanding of computer organization/architecture is preferred.
• Strong analytical/problem solving skills and pronounced attention to details.

ACADEMIC CREDENTIALS:

• Qualification: Bachelors or Masters in Electrical/Electronics Engineering

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