Company Overview

Proxelera’s unmatched expertise in VLSI design is expanding into new frontiers in the international market. Our business operations are making an entry into the Israeli market aggressively, heralding a new milestone. In this regard, we have signed up with the Israeli company, TechLink Global Ltd, based out of Tel Aviv. Proxelera’s presence in one of the most technologically advanced countries in the world stands as a testimony to our technical prowess in the VLSI and semiconductor industry. The headquarter located in Bangalore. The company belongs to the Semiconductors industry.

Company Website

Job Overview

We are looking for a skilled AMS Layout Engineer to join our dynamic team at Proxelera. This is a full-time, mid-level position based in either Bengaluru or Hyderabad. The ideal candidate will have a minimum of 4 years of work experience in Analog Layout Design (Mandatory skill) and will be proficient in various other skills required for the role.

Qualifications and Skills

• Minimum of 4 years of experience in Analog Layout Design (Mandatory skill).
• Proficiency with Cadence Virtuoso is essential for this role.
• Strong understanding of Physical Design practices and procedures.
• Experience with Layout Automation techniques and tools.
• Hands-on experience with DRC/LVS Verification processes.
• Knowledge of Floorplanning for integrated circuit design projects.
• Experience with Parasitic Extraction techniques.
• Ability to perform Signal Integrity Analysis to ensure design robustness.
• Experience in the layout of a wide variety of circuit types is required: i.e., High-speed circuits, ESD, Amplifiers, Drivers, PLLs, Bandgap, Equalizer, CDR, Serdes, LDOs, PLLs etc.,
• Knowledge of common circuit layout practices such as: matching techniques, ESD/Latch-up mitigation techniques, Antenna, LDE, EMIR and circuit parasitic reduction etc.,

Roles and Responsibilities

• Design and layout of analog and mixed-signal circuits using Cadence Virtuoso.
• Ensure DRC (Design Rule Check) and LVS (Layout Versus Schematic) compliance.
• Collaborate with design engineers to meet project specifications and timelines.
• Improve layout automation processes to enhance design efficiency.
• Conduct floorplanning to optimize space and performance of the integrated circuits.
• Perform parasitic extraction to evaluate and minimize unwanted parasitics.
• Execute signal integrity analysis to ensure optimal circuit performance.
• Participate in design reviews and provide technical feedback to team members.