Skills for Design Verification Engineer

Desired skills for design verification engineer include:

Perl

System Verilog

Assertion based formal verification will be

UVM

Verilog

C

TCL

Industry standard interfaces

One of the scripting languages: Python

Formal verification methodology

Desired experience for design verification engineer includes:

Be an active Beta user to understand potential issues that users may face

MS in EE, CS, CSE with ideally/preferred 1-2 years industry experience

Background and interest in computer graphics, Direct3D, OpenGL, DirectCompute, or OpenCL a plus

BS/MS in EE, CS, CSE plus a minimum 4 years hardware design or verification experience

Experience with functional modeling using C++ and SystemC preferred

Experience with build tools including make, version control, LSF, Perl, or Ruby preferred