Physical Design Engineer
Physical Design Engineer58
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58
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About the Job
Skills
Job Title: Physicla design Implementation
Location: Banglore
Job Overview: We are seeking an exceptional PD Implementation Engineer to take a key role in our semiconductor design team. As a PD Implementation Engineer, you will development and implementation of cutting-edge physical design methodologies and flows for complex ASIC designs, and did block level implementation. You will collaborate closely with cross-functional teams to ensure the successful delivery of high-quality designs.
Responsibilities:
- Perform Synthesis, floorplanning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs.
- Define and drive physical design strategies to meet aggressive performance, power, and area targets.
- Perform efficient Clock planning and distribution to entire grid with the use of Mesh or CTS.
- Conduct detailed analysis of timing, power, and area, and drive design optimizations to improve QoR.
- Signoff closure support for STA, PV, LEC, IR/EM, CLP very efficiently.
- Work closely with RTL design and DFT teams to understand design requirements and constraints, and drive successful tapout of complex designs.
- Support and Development of advanced physical design methodologies and flows for complex semiconductor designs.
Requirements:
- Bachelor's or Master's degree in Electrical Engineering or Electronics & Communications.
- Proficiency in industry-standard EDA tools from Cadence, Synopsys and Mentor Graphics for Synthesis, PnR, Signoff Closure.
- Strong scripting skills using TCL, Python, or Perl for design automation and tool customization.
- Excellent problem-solving and analytical skills, with a track record of delivering high-quality designs on schedule.
- Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment.
- Proven ability to Engineer and mentor junior engineers, fostering their professional growth and development.
Preferred qualifications:
- Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology.
- Expertise in Synthesis that includes details understanding of RTL, Early PnR timing issues, Constraint issue, design issues.
- Experience in handling Partitions and blocks for size estimation, pin assignment, CTS.
- Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for PD integration at block level.
- Detailed Knowledge on Clocking methodology and various techniques to improve skew, latency, timing, power.
- Familiarity with low-power design techniques and methodologies, such as multi-voltage domains and power gating using UPF.
- Expertise in physical verification, including DRC, Antenna, LVS, LEC and ERC checks.
- Expertise in Timing Closure including setup, hold, DRV, SI, Interface issues.
- Experience and good understanding in various foundries and their Backend implementation requirement.
If you are interested send me your resume to yaswanth.bollu@eximietas.design
About the company
Industry
Engineering Services
Company Size
201-500 Employees
Headquarter
San Jose, California
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