About Eximietas:

https://www.eximietas.design/

Eximietas, a technology services and solutions company headquartered in San Jose, CA with a global footprint that extends to Bangalore, Chennai and Bhubaneswar in India. Eximietas Design is a leading technology firm specializing in [VLSI/Cloud Computing/Cyber Security/AI/ML] solutions. With a commitment to innovation and excellence, we empower businesses to thrive in the dynamic digital landscape. Our success is fuelled by the expertise of our engineering leadership team, drawn from industry giants such as Google, Cisco, Microsoft, Oracle, Uber, Broadcom, and Sun.

Position: Design for Test Engineer/ Lead

This job might be for you if:

• You enjoy solving problems. You love taking on difficult challenges and finding creative solutions.

• You don’t know the answer but will dig until you find it.

• You communicate clearly. You write well.

• You are motivated and driven. You volunteer for new challenges without waiting to be asked. You will take ownership of the time you spend with us and make a difference.

• You can impress our customers with your enthusiasm to solve their issues (and solve them!)

Job Overview:

We are seeking an experienced and highly skilled Senior SOC Design for Test Engineer with a

minimum of 5 years of hands-on experience in SOC Design for Test. As a key member of our team, you will play a pivotal role in ensuring the testability, manufacturability, and quality of our cutting-edge System on Chip designs.

Job Description:

• Lead and manage SOC Design for Test efforts for complex projects, ensuring the successful execution coverage, manufacturability, and quality plans.

• Develop full chip and block level DFT implementation from the DFx Specifications and product coverage, quality, and manufacturability goals. Define and implement Test controllers at top level and block level, fuse controllers, test clocking strategy, chip I/O test strategy and HSIO test strategy.

• Define JTAG TAP, boundary scan, I/O Test JTAG access, IEEE1687 iJTAG network and instrument design and implementation. Define the Test Interface for each of the P&R IP blocks for Scan, MBIST and other test interfaces.

• Define hierarchical block isolation, Test clocking and On Chip Clock controllers and reset methodology. Define scan and MBIST timing at the top level and block level timing.

• Analyse block level RTL or gates to ensure that scalability and coverage is satisfied as per the design goals. Ensure that DFT is provided to fix the DFT violations to ensure that the design goals are meet.

• Analyse compression requirements for each of the blocks, define Intest and Extest compression requirements and define the requirements for compression engines. Synthesize compression engines for each of the blocks. Create the collaterals for compression for the IPs.

• Block level scan insertion as well as development of the scan wrappers for the blocks. Do scan insertion on the blocks, analyse scan DRC, implement DFT fixes. Create scan protocol files for designs, create scan inserted netlist, create scan definitions as well as scan definition files for PD. Perform ATPG on the scan inserted netlist, analyse DRC and coverage violations.

• Deep knowledge of different scan models Stuck-at, transition test, path-delay, bridging, cell aware, small-delay transition, IDDQ test etc. Ability to analyse coverage for each of the model types.

• Running GLS with or without timing for the scan vectors. Ability to debug the failures and working with timing and PD teams to fix the timing issues.

• Understanding of pattern delivery to the post-silicon test engineering teams. Delivering to the Test engineering the Test pin muxing and other full chip requirements for the Test Engineering Team. Understanding tester requirements and delivering the patterns in the formats that the tester teams needs.

• Implement pattern retargeting. Create grey box models for blocks. Coverage analysis of full chip consolidating Intest and Extest patterns. Knowledge of Top level scan architecture and creating flow to create pattern retargeting.

• Knowledge of Streaming Scan Network and other Top level scan pin sharing and implementing the block to top level pattern generation for this flow.

• Implementing Memory Testing and MBIST. Knowledge of Memory defect models and test algorithms. Knowledge of memory bit mapping and redundancy analysis. Implementing memory repair and fuse sharing among various memory.

• Knowledge of LogicBIST with Test point insertion, X-blocking.

• Full chip DFT delivery for tapeout including but not limited to DFT netlist verification, pattern delivery, Tester requirements.

• Debug DFT patterns post silicon, ability to analyse chain test patterns for failures, scan pattern failures. Analyse MBIST pattern failures, yield and repair debug.

• Ability to perform volume diagnostics on the parts to isolate and improve the patterns.

Qualifications:

• Bachelor’s degree in computer science, Electrical/Electronics Engineering, or related field. OR Master’s degree in computer science, Electrical/Electronics Engineering, or related field. OR PhD in Computer Science, Electrical/Electronics Engineering, or related field.

• 5+ years of hands-on experience in SOC Design for Test.

• Expertise in DFT tools and flows in scan intertion, ATPG, GLS simulation, diagnosis flows.

• Prior experience working on IP level and SOC level DFT projects.

• Proficient in DFT tools from Siemens (Tessent), Synopsys DFTmax, Tetramax, Spyglass DFT advisor, Genius DFT, Modus, VCS, Xcelium etc.

• Worked in full chip design or complex IP delivery in the area of DFT.

• Experience in post silicon debug, diagnosis and yield enhancements is a plus.