Design Verification

(Preferred Location HYD)

Lead (8-20yrs): 1 Opening

Engineers (3-5yrs): 20 opening

Sr. Engineers(5-7yrs): 5 Openings

Reference JD:

•  Experience in SOC/IP/ASIC/GLS Functional Verification

•  He/she will be involved in developing testbench for the block/cluster, testcases, test plans and functional and code coverage.

•  Knowledge of Industry standard protocols –Ethernet, PCIE, USB, DRR3/4, AXI, AHB and low speed peripherals, etc.

•  Knowledge of Clocking, Boot/Reset flows.

•  Experience with System Verilog/OVM/UVM SOC development environment is must

•  Experience with Low power/UPF verification techniques.

•  Strong background in scripting - PERL, TCL, Python.

•  Understanding of software and/or hardware validation techniques