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Physical Design Engineer

Bangalore
Full-Time
Mid-Level: 4 to 6 years
โ‚น 3L - โ‚น 6L (Per Year)
Posted on Feb 21 2024

About the Job

Skills

Physical design
PD
ADM
P&R
STA
ECO

๐„๐ฑ๐œ๐ข๐ญ๐ข๐ง๐  ๐Ž๐ฉ๐ฉ๐จ๐ซ๐ญ๐ฎ๐ง๐ข๐ญ๐ฒ ๐Ÿ๐จ๐ซ ๐’๐ž๐ง๐ข๐จ๐ซ ๐๐ก๐ฒ๐ฌ๐ข๐œ๐š๐ฅ ๐ƒ๐ž๐ฌ๐ข๐ ๐ง ๐„๐ง๐ ๐ข๐ง๐ž๐ž๐ซ๐ฌ!

Hiring at ARF Design


Job Title: Physical Design Engineer

Experience: Level: 5+ Years.

Location: Bangalore


Job Type: Full-time


๐‰๐จ๐› ๐ƒ๐ž๐ฌ๐œ๐ซ๐ข๐ฉ๐ญ๐ข๐จ๐ง:

We are urgently seeking a highly skilled and

Physical Design Engineer with a minimum of 5 years of hands-on expertise in the semiconductor industry.


๐‘๐ž๐ฌ๐ฉ๐จ๐ง๐ฌ๐ข๐›๐ข๐ฅ๐ข๐ญ๐ข๐ž๐ฌ:

  • Manage tapeout cycles for multiple chips, demonstrating proficiency in the complete Physical Design (PD) life cycle.
  • Execute Engineering Change Orders (ECOs) throughout the design process.
  • Implement clock-tree synthesis and contribute to power-aware PD flows (ADM, P&R, etc.).
  • Drive PD-STA and ensure timing constraints are met.
  • Lead multi-mode, multi-corner timing closure efforts.


๐‘๐ž๐ช๐ฎ๐ข๐ซ๐ž๐ฆ๐ž๐ง๐ญ๐ฌ:

  • Bachelor's/master's degree in electrical engineering or related field.
  • 5+ years of experience in Physical Design for semiconductor chips.
  • In-depth knowledge of ECO life cycle and clock-tree synthesis.
  • Expertise in power-aware PD flows, including ADM and P&R.
  • Proficient in PD-STA and timing constraint management.
  • Proven track record of successful multi-mode, multi-corner timing closure.


๐‡๐จ๐ฐ ๐ญ๐จ ๐€๐ฉ๐ฉ๐ฅ๐ฒ:

Interested candidates are invited to submit their resume to

poojakarve@arf-design.com.

Please include "Senior PD Engineer" Application in the subject line.

About the company

Semiconductor Industry

Industry

Semiconductors

Company Size

201-500 Employees

Headquarter

Bangalore

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