Hi,

We are Hiring STA Engineer for our client VLSI design services to the OEM’s, ODM’s & chipmakers Company located in Bangalore.

• Interview Process - One or two round of internal interviews and then HR 
• Max Budget for each role - 4X
• Number of working days- 5 Days
• NP : Immediate or 30days

JD: 

• Very good understanding of timing concepts
• Should have a good understanding of SDC and constraints syntax
• Work with the design and implementation teams to develop and qualify timing constraints
• Experience in Timing Analysis both at block level and SoC level
• Experience with Industry Timing signoff tools like Primetime / Tempus is a must
• Experience in DMSA or Tweaker
• Should have a good understanding of different Timing modes and Corners
• Experience in MMMC
• Work closely with the physical design engineers to resolve implementation related timing issues
• Should be able to plan and track self-execution and report result on regular basis systematically
• Should be able to solve timing challenges in Block/SOC by manually closing difficult paths
• Should have a clear understanding of Crosstalk delay/noise, Timing derates, AOCV/POCV concepts and its impact of design closure
• Should have worked on Timing ECO generation in multi-voltage designs
• Experience Timing & Noise Signoff Closure at block level or Full chip-level on advanced process nodes
• Hands on scripting skills on TCL / Perl.

Expectations from the Role

• Excellent debugging and problem-solving skills
• Effective communication skills to interact with all stakeholders
• Must be highly focused and remain committed to obtaining closure on project goals.
• Ability to work independently and complete work assigned
• Should possess good Leadership Skills
• Should have a Go-getter attitude

Mandatory skills

> SDC and constraints syntax

>Timing signoff tools like Primetime / Tempus is a must

>MMMC, DMSA or Tweaker

>Block /SOC,AOCV/POCV, TCL / Perl.