Hi,

We are Hiring PV Engineer for our client VLSI design services to the OEM’s, ODM’s & chipmakers Company located in Bangalore.

• Interview Process - One or two round of internal interviews and then HR 
• Max Budget for each role - 4X
• Number of working days- 5 Days
• NP : Immediate or 30days

Job Responsibilities: 

Responsible for Full-chip Physical Verification Sign-off in the area of (DRC, LVS, ANT, ERC, ESD, PERC) for tape-out.

Co-work with the Place & Route team to resolve full-chip layout integration issues.

Coordinates with internal IP owners on IP related issues.

Coordinates with the Manufacturing Team on DRC related issues.

Provide automation solutions to improve efficiency in tape-out flow.

Report on tapeout issues

Requirements: 

Bachelor/Master’s Degree in Electrical/Electronic Engineering / Computer Science or equivalent

With minimum 5 years of relevant experience

Familiar with IC Design front-to-backend flow

Preferably well-versed in Calibre ICV.

Proficient in script programming, such as, Tcl, Perl or C-shell

Proficient in UNIX (Linux) platforms

Strong communication skills, problem solving and analytical skills

Mandatory skills

1. C-shell
2. IC Design front-to-backend flow
3. Tcl, Perl
4. UNIX (Linux)