Hi,

We are hiring for our client, a Semi conductor industry in Coimbatore location

Job Description:

Department Name - ATE TESTING

Qualification Bachelor’s or Master’s degree in related discipline

Roles and Responsibilities

· Working on 10nm/7nm/5nm or lower nodes designs with various customers for deployment.

· Expertise in solving customer's problems for critical designs to achieve desired performance, area, and

power targets.

· Responsible to develop flow and methodology for doing placement, CTS, and routing.

· Work closely with RTL design and DFT teams to understand design requirements and constraints, and

drive successful tape-out of designs.

· Provide training and technical support to customers.

Required Technical and Professional Expertise:

· Experience on hierarchical designs and/or Low Power implementation is an advantage.

· Performing physical implementation of blocks from gate netlist to GDSII.

· Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for PD

integration.

· Experience on Synthesis, interfacing with RTL and implementation designers to achieve better quality of

results.

· Experience on Floorplan design, including placement of hard macros, padring, power grid and custom

analog routes.

· Solid experience in place & route flow (placement guidelines, clock-tree synthesis, routing, timing

optimizations).

· Detailed Knowledge on Clocking methodology and various techniques to improve skew, latency, timing,

power.

· Block/Partition signoff closure for STA, PV, LEC, IR/EM, CLP very efficiently.

· Experience on Static Timing Analysis related activities (constraints development, parasitic extractions,

sign-off requirements).

· Familiarity with low-power design techniques and methodologies, such as multi-voltage domains and

power gating using UPF.

· Expertise in physical verification, including DRC, Antenna, LVS, PERC, and ERC checks.

· Expertise in Timing Closure including setup, hold, DRV, SI, Interface issues.

· Knowledge of emerging technologies such as machine learning and AI for design automation and

optimization.

· Hands-on experience with FinFET technologies is an advantage

· Strong scripting skills using TCL, Python, or Perl for design automation and tool customization.

· Proficiency in industry-standard EDA tools from Cadence, Synopsys and Mentor Graphics for Synthesis,

PnR, Signoff Closure.